1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular to a semiconductor memory device provided with memory cells that are configured by one data storage capacitor and two switching elements.
2. Description of Related Art
Memory cells each of which is configured by one data storage capacitor, and one switching element (transistor), are known as dynamic random access memory (DRAM) cells. The memory cells are referred to as “one-transistor/one-capacitor (1T/1C)” memory cells. Data access to 1T/1C memory cell is performed by using the one transistor and the refresh is performed by using the same transistor. Accordingly, data access to a memory cell on a bit line cannot be performed for a period during which the refresh is performed to a memory cell on the same bit line. High speed access to the memory is thus difficult.
In contrast to the 1T/1C memory cell, a two-transistor/one-capacitor (2T/1C) memory cell in which two switching elements (transistors) are connected to one capacitor has been proposed. Such a memory cell is disclosed in Japanese Patent Laid-Open Application No. 2000-124331. As shown in FIG. 10, drains of a first MOS transistor Tr1 and a second MOS transistor Tr2 are connected to one capacitor C. A first bit line B1 is connected to a source of the first MOS transistor Tr1, and a second bit line B2 is connected to a source of the second MOS transistor Tr2. Further, a first word line W1 is connected to a gate of the first MOS transistor Tr1, and a second word line W2 is connected to a gate of the second MOS transistor Tr2. In such 2T/1C memory cell M, if one of the transistors Tr1 and Tr2 is used for data write-in and the other transistor is used for data read-out, then data write-in and data read-out can be performed at the same timing to different memory cells on the same bit line. Alternatively, if one of the transistors Tr1 and Tr2 is used for data write-in and data read-out, and the other transistor is used for refresh, then data write-in, data read-out, and refresh can be performed at the same timing to different memory cells on the same bit line. It thus becomes possible to achieve high speed access to the memory cells.
A layout structure of 2T/1C memory cell is proposed in JP2000-124331. As shown in FIG. 11, an active region DA extends in a diagonal direction with respect to the word lines and the bit lines, which are mutually orthogonal. The first MOS transistor Tr1 and the second MOS transistor Tr2 are configured by the first word lines W1 and the second word lines W2 within the active region DA. Each of the MOS transistors Tr1 and Tr2 is connected to the first bit line B1 and to the second bit line B2, through bit line contacts BC. It should be noted that “active region” in this specification means a region that is formed on a semiconductor substrate, surrounded by an element separation region, in which diffusion layers, and a channel region that is sandwiched by the diffusion layers, are formed in order to configure a memory cell. Furthermore, A capacitor contact CC is provided in the diffusion layer shared by the first and second transistors Tr1 and Tr2 and is connected to a capacitor. The active regions DA of adjacent memory cells are formed in a zigzag pattern and are mutually continuous so that the plurality of memory cells arranged in a bit line direction are connected to the first bit line B1 and the second bit line B2.
Alternatively, a configuration disclosed in FIG. 1 of JP 2000-124331, but not shown here, has also been proposed. In this configuration, the active regions take on a different shape having a bent portion like that of a crank. A configuration disclosed in FIG. 8 of JP 2000-124331 has also been proposed. In this configuration, the diffusion layers of the plurality of memory cells that are arranged along the bit lines are formed in a linear shape extending in a direction that is parallel to the bit lines. Branch lines protrude out from the bit lines and are connected to the MOS transistors of each memory cell.
The Zigzag shape of the active regions DA as shown in FIG. 11 accompanies bent portions X in an outer edge of the active region pattern. The active regions DA may easily lose their shape in the bent portions X when the active regions are formed in the semiconductor substrate by using a photolithography technique, and it is difficult to form the active regions into shapes as designed. In addition, stress tends to be caused in the semiconductor substrate in the portions that have lost their shape. In particular, an angular portion of the active region may become rounded, and the width dimension of the active region in this portion may decrease. If this loss of shape is caused in the active regions, a target gate width will not be obtained. Further, electrical leakage fluctuation may be caused between the semiconductor substrate and the diffusion layers within the active regions due to stress. The problem may cause the decline of MOS transistor performance and deterioration of data retention characteristics of the memory cells. Accordingly, it is necessary to consider loss of shape of the active layers and stress, and design the active regions with a certain margin therefor. This becomes an impediment in miniaturizing the active regions, namely, an impediment in miniaturizing the memory cells.
Further, the layout structure cited in FIG. 1 of JP 2000-124331 has the same problems due to its bent portion. On the other hand, there are no bent portions in the active regions in the layout structure cited in FIG. 8 of JP 2000-124331. With the layout structure, although the problems that accompany the bent portions are eliminated, the branch lines extending from the bit lines must be formed, and contact failures will be caused and the securing the margin is needed due to loss of shape in the branch lines. As a result, impediments in miniaturizing the memory cells cannot be avoided.
In addition, in the layout structure shown in FIG. 11, each capacitor CC of adjacent memory cells has a narrower spacing in the bit line direction than in the word line direction. Accordingly, if one tries to increase the planar surface area of the capacitors formed on an upper layer of the MOS transistors in order to increase the data storage volume, the planar shape of the capacitors cannot simply be made into a rectangular shape having one long side. As a result, the planar shape of the capacitors becomes complex, and there is a problem in that manufacturing of capacitors is difficult.